Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large-scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and the quality of individual substrates and dies.
Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed. It is used in a wide variety of commercial and military electronic devices and equipment. To store information, flash memory includes an addressable array of memory cells, typically made from floating gate transistors. Common types of flash memory cells include stacked gate memory cells and split gate memory cells. Split gate memory cells have several advantages over stacked gate memory cells, such as lower power consumption, higher injection efficiency, less susceptibility to short channel effects, and over erase immunity.
However, as the device dimensions continue to be scaled down, short distance among the gate memory cells may result in current leakage. Thus, proper management of the distances and dimensions among the gate memory cells is desired to provide the device structures with desired electrical performance.